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HA16150T/P
High-Speed Current Mode Push-Pull PWM Control IC
REJ03F0146-0300 Rev.3.00 Jan 30, 2007
Description
The HA16150 is a high-speed current mode PWM control IC with push-pull dual outputs, suitable for high-reliability, high-efficiency, high-mounting-density isolated DC-DC converter and high-output AC-DC converter control. The HA16150 can be used in various applications, including push-pull converters and half-bridge, double-forward, and single-forward applications. The HA16150 incorporates 180-degree phase-inverted push-pull dual outputs, and directly drives a power MOS FET. Operation at a maximum of 1 MHz is possible on an oscillator reference frequency. The package lineup comprises an ultra-thin surface-mount TSSOP-16 suitable for slim communication system modules, and a general-purpose insertion DILP-6 suitable for characteristics evaluation.
Features
Supply voltage Vcc: 20 V Peak output current Ipk-out: 1.0 A Operating junction temperature Tjopr: -40C to +125C VREF output voltage VREF: 5.0 V 1% UVLO start threshold VH: 9.3 V 0.7 V UVLO shutdown threshold VL: 8.3 V 0.7 V Operating current Icc: 4 mA typ. Standby current Is: 150 A typ. Soft start (one external timing capacitance) Remote on/off control Independent dead band time adjustment Current limiter adjustment (set drooping characteristic adjustment) Push-pull/single-end output switching Package lineup: TSSOP-16/DILP-16
Rev.3.00 Jan 30, 2007 page 1 of 24
HA16150T/P
Pin Arrangement
INP INM EOUT CSLIM CS RT CT SS 1 2 3 4 5 6 7 8 (Top view) 16 15 14 13 12 11 10 9 VREF REMOTE VCC OUT2 PGND OUT1 TDB SGND
Pin Functions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 INP INM EOUT CSLIM CS RT CT SS SGND TDB OUT1 PGND OUT2 VCC REMOTE VREF Pin Name Pin Functions Error amplifier non-inverted (+) input Error amplifier inverted (-) input Error amplifier output Current limiter level adjustment Current sense signal input Operating frequency setting resistance connection Operating frequency setting capacitance connection Soft start time setting timing capacitance connection Small signal system ground Dead band time setting timing capacitance connection Power MOS FET driver output 1 Power system ground Power MOS FET driver output 2 Supply voltage Remote on/off control Reference voltage
Rev.3.00 Jan 30, 2007 page 2 of 24
HA16150T/P
Block Diagram
VREF 16 VCC 14
VREF
22.2V Vref Generator REMOTE 15
REMOTE Comp. UVL 300A
UVL
TDB Comp.
Vref Good
R Q Q
Vref good
0.5V
VREF 5A
1.1V
Vref good
S
Single End Comp.
10 TDB
S Q Q
SS 8
SS Comp.
Vref good
SS Ramp CT SS Ramp
R
TDB Latch
4V
Vcc
11 OUT1
PGND VREF
VREF
RT 6
D Q
Driver
Vcc
CT 7
CK Q
1/2 Divider
Vref good
13 OUT2 12 PGND
R S Q Q
Oscillator
Blanking Pulse
IN
Vcc
CS Latch
OUT 65ns
VREF
5 CS CS Comp. 2R R 9 SGND
400A INM 2 E-Amp. INP 1 1.4V 3 EOUT 4 CSLIM
(VCOMP-2VF)/3
Blanking Enable Comp.
Rev.3.00 Jan 30, 2007 page 3 of 24
HA16150T/P
Absolute Maximum Ratings
(Ta = 25C)
Item Power supply voltage OUT1 output current (peak) OUT2 output current (peak) OUT1 output current (DC) OUT2 output current (DC) OUT1 output voltage OUT2 output voltage INM pin voltage REMOTE pin voltage REMOTE pin current INP pin voltage SS pin voltage RT pin voltage RT pin current CT pin voltage CSLIM pin voltage EOUT pin voltage VREF pin voltage TDB pin voltage CS pin voltage Operating junction temperature Symbol Vcc Ipk-out1 Ipk-out2 Idc-out1 Idc-out2 Vout1 Vout2 Vinm Vremote Iremote Vinp Vss Vrt Irt Vct Vcslim Veout Vref Vtdb Vcs Tj-opr Ratings 20 1.0 1.0 0.1 0.1 -0.3 to Vcc -0.3 to Vcc -0.3 to Vcc -0.3 to Vcc +0.2 -0.3 to Vcc -0.3 to Vref -0.3 to Vref -0.2 -0.3 to Vref -0.3 to Vref -0.3 to Vref -0.3 to Vref -0.3 to Vref -0.3 to Vref -40 to +125 Unit V A A A A V V V V mA V V V mA V V V V V V C C 4 3 3 Note
Storage temperature Tstg -55 to +150 Notes: 1. Rated voltages are with reference to the GND (SGND, PGND) pin. 2. For rated currents, inflow to the IC is indicated by (+), and outflow by (-). 3. Shows the transient current when driving a capacitive load. 4. HA16150T (TSSOP): ja = 250C/W This value is based on actual measurements on a 110% wiring density glass epoxy circuit board (55 mm x 45 mm x 1.6 mm). HA16150P (DILP): ja = 124C/W
Rev.3.00 Jan 30, 2007 page 4 of 24
HA16150T/P
Electrical Characteristics
(Ta = 25C, Vcc = 12 V, Fosc = 100 kHz)
Supply Item Start threshold Shutdown threshold UVLO hysteresis Start-up current Operating current Vcc zenner shunt voltage Vz temperature stability VREF Output voltage Line regulation Load regulation Temperature stability Oscillator Oscillator frequency Temperature stability PWM Comparator Error amplifier High voltage Low voltage Differential voltage Input bias current Open loop gain EOUT sink current EOUT source current Low voltage Current sense High voltage Voltage gain Delay to output Leading edge blanking time Leading edge blanking disable voltage On threshold voltage Off threshold voltage Sink current Symbol VH VL dVUVL Is Icc Vz dVz/dTa Vref Vref-line Vref-load dVref/dTa fosc dfosc/dTa Vth Vtl dVt Ifb Av Isnk-eout Isrc-eout Vol-eout Voh-eout Avcs td-cs tbl Min 8.6 7.6 0.7 100 - 21.2 - 4.95 - - - 88 - - - - -1 - - - - 4.7 2.85 - - Typ 9.3 8.3 1.0 150 4 22.2 4.5 5.0 5 5 80 100 0.1 3.0 2.0 1.0 - 70 3.0 -0.4 0.8 5.0 3.00 150 65 Max 10.0 9.0 1.3 250 6 23.2 - 5.05 20 20 - 112 - - - - +1 - - - 1.1 - 3.15 230 - Unit V V V A mA V mV/C V mV mV ppm/C kHz %/C V V V A dB mA mA V V V/V ns ns Vcc = 8V Vinm = 1.0V, Vinp = 1.25V, Vcs = 0V Icc = 10mA Icc = 10mA *
1
Test Conditions
Iref = -1mA Vcc = 11V to 18V Iref = -1mA to -20mA Ta = -40 to 125C Measured at OUT1 and OUT2 RT = 27k, CT = 1000pF 1 Ta = -40 to 125C * DC * 1 DC * DC *
1 1
f = 1.0kHz * 1 Veout = 1.1V * Veout = 3.0V * EOUT : Open EOUT : Open
1
1
*
1
Vbl-off
1.3
1.4
1.5
V
Measured pin : EOUT
Remote
Von Voff Iremote
1.40 - 60 -7.0
- - 90 -5.0
- 3.00 120 -3.0
V V A A
* *
1
1
Vremote = 4V Vss = 1V
Soft start Source current Iss Note: 1. Reference values for design.
Rev.3.00 Jan 30, 2007 page 5 of 24
HA16150T/P
Electrical Characteristics (cont.)
(Ta = 25C, Vcc = 12 V, Fosc = 100 kHz)
OUT1 Item Minimum duty cycle Maximum duty cycle Rise time Fall time Low voltage High voltage OUT2 Minimum duty cycle Maximum duty cycle Rise time Fall time Low voltage High voltage Dead-band time Note: Dead-band time Symbol Dmin-out1 Dmax-out1 tr-out1 tf-out1 Vol1-out1 Vol2-out1 Voh1-out1 Voh2-out1 Dmin-out2 Dmax-out2 tr-out2 tf-out2 Vol1-out2 Vol2-out2 Voh1-out2 Voh2-out2 tdb0 Min - 48 - - - - 11.5 10.0 - 48 - - - - 11.5 10.0 - - Typ - 49 30 30 0.05 0.5 11.9 11.0 - 49 30 30 0.05 0.5 11.9 11.0 60 140 Max 0 - 65 65 0.2 2.0 - - 0 - 65 65 0.2 2.0 - - - - Unit % % ns ns V V V V % % ns ns V V V V ns ns Test Conditions Veout = 0V TDB : OPEN CL = 1000pF CL = 1000pF Iout = 20mA Iout = 200mA (pulse) Iout = -20mA Iout = -200mA (pulse) Veout = 0V TDB : OPEN CL = 1000pF CL = 1000pF Iout = 20mA Iout = 200mA (pulse) Iout = -20mA Iout = -200mA (pulse) 1 TDB : OPEN * Ctdb = 47pF *
1
tdb 1. Reference values for design.
Rev.3.00 Jan 30, 2007 page 6 of 24
HA16150T/P
Timing Diagram
1. Start-up Timing
9.3V VCC 8.3V
VREF 3V V_CT 2V
RESET
(internal signal)
Q
(internal signal)
Q
(internal signal)
V_TDB term.
V_TDB comp. out
(internal signal)
tdb Dead-band pulse
(internal signal)
tdb
OUT1
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OUT2
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
OFF
ON
Rev.3.00 Jan 30, 2007 page 7 of 24
HA16150T/P 2. Current Sense
VREF 3V V_CT 2V
RESET
(internal signal)
Dead-band pulse
(internal signal)
Q
(internal signal)
Q
(internal signal)
V_EOUT V_CS V_CS comp.(-)
V_CS comp.(-) = (V_EOUT - 2VF) / 3
OUT1
OUT2
Rev.3.00 Jan 30, 2007 page 8 of 24
HA16150T/P 3. Soft Start
VREF 3V V_CT 2V
RESET
(internal signal)
V_TDB term.
Dead-band pulse
(internal signal)
V_SS
SS comp. IN+
(internal signal)
SS comp. out
(internal signal)
OUT1
OUT2
Rev.3.00 Jan 30, 2007 page 9 of 24
HA16150T/P 4. Leading Edge Blanking
3V V_CT 2V
RESET
(internal signal)
Dead-band pulse
(internal signal)
Q
(internal signal)
Q
(internal signal)
V_EOUT
V_CS
1.4V Blanking Time reset
V_CS comp.(-)
(internal signal)
Blanking pulse
(internal signal)
V_CS comp.(+)
(internal signal)
OUT1
OUT2
Rev.3.00 Jan 30, 2007 page 10 of 24
HA16150T/P 5. Push-Pull/Single-End Switching (1) Push-pull operation: Leave the TDB pin open or connect a capacitance to GND
3V V_CT 2V RESET
(internal signal)
V_TDB term.
Dead-band pulse
(internal signal)
OUT1
OUT2
(2) Single-end operation: Perform pull-up connection of the TDB pin to the VREF pin
3V V_CT 2V RESET
(internal signal)
5V V_TDB term.
Dead-band pulse
(internal signal)
0V OUT1
OUT2 0V
Rev.3.00 Jan 30, 2007 page 11 of 24
HA16150T/P
Functional Description
1. UVL Circuit The UVL circuit monitors the Vcc voltage and halts operation of the IC in the event of a low voltage. The voltage for detecting Vcc has a hysteresis characteristic, with 9.3 V as the start threshold and 8.3 V as the shutdown threshold. When the IC has been halted by the UVL circuit, control is performed to fix driver circuit output low, halt VREF output and the oscillator, and reset the soft start circuit.
9.3V 8.3V
VCC
VREF
4.5V 3V
4.5V
V_CT
2V
V_SS
OUT1
OUT2
Figure 1 2. Remote ON/OFF Circuit A remote on/off control function is incorporated, enabling the IC to be halted without cutting the supply voltage by pulling the REMOTE pin up to 3.0 V or higher. This function halts VREF output and driver output. At this time the IC enters Remote-OFF mode and IC current dissipation can be decreased. This function can thus be used for power management, etc. When remote off control is performed, the soft start circuit is also reset, and therefore a soft start is effected when restarting, preventing overshoot. However, when restarting by the remote on control function before the SS pin is completely discharged, soft start operation may not be performed normally. In such a case, add a circuit to pull the SS pin out in conjunction with a remote off signal.
SS
REMOTE 100k
Figure 2 Example of Circuit to Pull out SS Pin
Rev.3.00 Jan 30, 2007 page 12 of 24
HA16150T/P If the remote on/off control function is not used, the REMOTE pin should be permanently pulled down to GND with a resistance of about 100 k. The remote on/off control function halts only reference voltage. Other functions will be stopped when the reference voltage is below 4.5 V (typ.). Large stabilizing capacitance of the VREF pin results in a difference between the timing of remote off signal and the timing to stop the IC
(1) VREF is halted by REMOTE.
4.5V(Typ)
(2) When VREF is blow 4.5 V(Typ), other functions are stopped.
CH3: REMOTE CH4: VREF CH1: SS CH2: OUT1
Figure 3 Operation When Remote is Off (Reference Data)
3. Soft Start Circuit This function gradually increases the pulse width of the OUT pin from 0% duty at start-up to prevent a sudden increase in the pulse width that may cause problems such as transient stress on external parts or overshoot of the secondary-side output voltage. The soft start time can easily be set with a single external capacitance.
V_CT
SS comp. IN+
(internal signal)
V_SS
1.1V
SS comp. out
OUT1
OUT2
Figure 4
Rev.3.00 Jan 30, 2007 page 13 of 24
HA16150T/P Soft start time tss is determined by SS pin connection capacitance Css and an internal constant, and can be estimated using the equation shown below. Soft start time tss is the time until the first pulse is output to the driver output OUT pin after VREF starts up following UVLO release. This is equivalent to the time until the SS pin voltage reaches IC-internal SS comparator reference voltage VTL (1.1 V), and can be calculated using the approximate equation shown below. Soft start time tss when Css is 1000pF is given by the following equation.
tss = Css x VTL = Iss
1000 [pF] x 1.1 [V] 5 [A]
220 [s] * Iss: SS pin source current, 5 A typ.
Note: A soft start circuit operates only once at the start-up of the IC (after the VREF pin voltage is launched and the VrefGOOD circuit is operated). If the SS pin is lowered to 1.1 V or less after the SS pin becomes once high, the pulse of OUT1 and OUT2 is not halt. Each duty cycle of OUT1 and OUT2 is fixed to 25%. 4. Dead Band Generation Circuit "Dead band" refers to the time when both push-pull dual outputs are off. By setting the dead band time arbitrarily, it is possible to configure a system in which the dual outputs are never on simultaneously with respect to input and load variations.
V_CT 0.5V
V_TDB
SS comp. out
(internal signal)
OUT1
OUT2
Figure 5 Dead band time tdb is determined by TDB pin connection capacitance Cdb and an internal constant, and can be estimated using the equation shown below. Even when the TDB pin is open, the dead band time does not become zero due to floating capacitance of the IC package, etc. This dead band time is designated tdb0. Dead band time tdb when Cdb is 47 pF is given by the following equation.
tdb = tdb0 +
47 [pF] x 0.5 [V] Cdb x Vth = tdb0 + 300 [A] Idb
= 60 [ns] + 78 [ns] = 138 [ns] * Idb: TDB pin source current, 300 A typ. * Vth: IC-internal TDB comparator reference voltage
Rev.3.00 Jan 30, 2007 page 14 of 24
HA16150T/P 5. Operating Frequency The operating frequency is adjusted by means of CT and RT. Adjustment examples are shown in the graph below. This graph shows driver output operating frequencies. The reference operating frequency generated at the CT pin is twice the driver output frequency. The driver output operating frequency can be estimated using the approximate equation shown below. This is only an approximate equation, and the higher the frequency, the greater will be the degree of error of the approximate equation due to the effects of CT pin voltage overshoot, undershoot and so forth. When the operating frequency is adjusted, it is essential to confirm operation using the actual system.
fosc = 8 8 = 3 x CT x RT 3 x C6 x R7 8 = 3 x 470 [pF] x 27 [k] = 210 [kHz]
10000
fosc (RT = 5.1k) fosc (RT = 10k) fosc (RT = 27k) fosc (RT = 75k)
1000
fosc (kHz)
100
0 100
1000 CT (pF)
10000
Figure 6
Rev.3.00 Jan 30, 2007 page 15 of 24
HA16150T/P 6. Current Limiter Level The drooping characteristic of the power supply output can be adjusted by adjusting the CSLIM pin voltage. For example, the drooping characteristic can easily be adjusted, as shown in the figure below, by setting VREF to a divided value with resistances R1 and R2 and connecting adjustment resistance Rx in parallel to R2.
R1 15k R2 12k
- +
E-amp.
2R
CS Comp.
Rx
R
3 EOUT
4 CSLIM
Figure 7 CSLIM Peripheral Circuit The graph below shows examples of power supply output drooping characteristic adjustment in a push-pull converter. As shown in this graph, the point at which the power supply output current limit begins to be applied can be adjusted by adjustment of the CSLIM pin voltage.
Rx: open (VCSLIM = 2.22V)
3.60 3.40 3.20
Rx: 24k (VCSLIM = 1.75V)
Rx: 33k (VCSLIM = 1.85V)
Vout (V)
3.00 2.80 2.60 2.40 2.20 2.00 0.0 2.0 4.0 Iout (A) 6.0
Rx: 15k (VCSLIM = 1.55V)
Rx: 47k (VCSLIM = 1.95V)
8.0
Figure 8 Adjustment of Power Supply Output Drooping Characteristic
Rev.3.00 Jan 30, 2007 page 16 of 24
- +
VREF
16
Vref
Vcc
5 CS
10.0
HA16150T/P
7. VREF Circuit
(1) For the VREF pin, make sure to connect stabilizing capacitance to GND. (2) When the value of stabilizing capacitance is small or the load of VREF pin is heavy, either OUT1 or OUT2 may be halted at high level if the IC is stopped by a remote off function. In such a case, increase the capacitance value. The minimum value of capacitance to be connected is approximated by the following equation.
Cref > 10s x (Iref + 6mA) 4.95V
(3) Depending on the value of capacitance to be connected, overshoot may result at the rising of the VREF pin (see the figure below). Take extra care when the VREF pin voltage is used as the power supply and reference voltage of external circuit.
1.0
Overshoot voltage (V)
0.8 0.6 0.4 0.2 0 1E-9
10E-9
100E-9
1E-6
10E-6
Vref pin capacitance (F)
Figure 9 Overshoot Voltage of Vref Pin (Reference Data)
8. CS Pin
RC filter is generally inserted into the CS pin to prevent the pin from malfunction due to noise. The CS pin has an internal circuit to pull out electric charge while both of the OUT1 and OUT2 are at the low level (dead band time). However, please be aware that the electric charge may not be pulled out when the duration of dead band time is short and the filter constant is not appropriate.
Rev.3.00 Jan 30, 2007 page 17 of 24
HA16150T/P
9. Usage on Half-bridge Power Supply
The HA16150 is operated in the current mode. However, the half-bridge power supply becomes unstable in principle by using current mode control. The HA16150, therefore, cannot be used basically. In order to use the HA16150 with the half-bridge power supply, add a circuit as shown below and operate the HA16150 in the voltage mode.
VREF R1 OUT1 C1 Q1 OUT2 C2 R2 Q2
CS input filter Vslope R3
Dead Band Time OUT1
1/fosc
OUT2 (CSLIM - 2VF) 3 CS
Figure 10 Example of Circuit for Voltage Mode Operation Design the charging circuits for R1 (R2), C1 (C2), Q1 (Q2) and R3 so that the peak voltage of CS is lower than (CSLIM-2VF)/3 at the maximum ON pulse width of OUT1 and OUT2. Furthermore, set the input filter values between R3 and CS pin so that the CS voltage is discharged assuredly while both of the OUT1 and OUT2 are at low level.
Rev.3.00 Jan 30, 2007 page 18 of 24
HA16150T/P
Characteristic Curves
Power Supply Current vs. Power Supply Voltage Characteristics 6.0 5.0 4.0
Icc (mA)
Ta = 25C fosc = 100kHz
3.0 2.0 1.0 0.0 7.0
7.5
8.0
8.5 Vcc (V)
9.0
9.5
10.0
Standby Current vs. Power Supply Voltage Characteristics 1.0 Ta = 25C fosc = 100kHz 0.8
Is (mA)
0.6
0.4
0.2
0.0
0
1
2
3
4
5 Vcc (V)
6
7
8
9
10
Rev.3.00 Jan 30, 2007 page 19 of 24
HA16150T/P
Power Supply Current vs. Power Supply Voltage (Clamp Zener Voltage) Characteristics 18.0 Ta = 25C 16.0 fosc = 100kHz 14.0
Icc (mA)
12.0 10.0 8.0 6.0 4.0 20.0
20.5
21.0
21.5 Vcc (V)
22.0
22.5
23.0
VREF Output Voltage vs. REMOTE Pin Voltage Characteristics 6.0 Ta = 25C 5.0 4.0
VREF (V)
3.0 2.0 1.0 0.0 0.0
0.5
1.0
1.5
2.0 VREMOTE (V)
2.5
3.0
3.5
4.0
Rev.3.00 Jan 30, 2007 page 20 of 24
HA16150T/P
VREF Output Voltage vs. Ambient Temperature Characteristics 5.20
Iref = 1mA
5.15 5.10
VREF (V)
5.05 5.00 4.95 4.90 4.85 4.80 -50 -25 0 25 Ta (C) 50 75 100 125
Operating Frequency vs. Ambient Temperature Characteristics 120
RT = 27k CT = 1000pF
110
fosc (kHz)
100
90
80 -50
-25
0
25 Ta (C)
50
75
100
125
Rev.3.00 Jan 30, 2007 page 21 of 24
HA16150T/P
UVL Start-up Voltage vs. Ambient Temperature Characteristics
10.0 9.8 9.6 9.4
VH (V)
9.2 9.0 8.8 8.6 8.4 8.2 8.0 -50 -25 0 25 Ta (C) 50 75 100 125
UVL Shutdown Voltage vs. Ambient Temperature Characteristics
9.0 8.8 8.6 8.4 8.2
VL (V)
8.0 7.8 7.6 7.4 7.2 7.0 -50 -25 0 25
Ta (C)
50
75
100
125
Rev.3.00 Jan 30, 2007 page 22 of 24
HA16150T/P
Application Circuit Example
The following diagram shows a sample application circuit for a push-pull converter with a 48 V input voltage, 3.3 V output voltage, and 10 A output current.
L2 1.5H
OUT(+)
R14 R18 680 390
R15 R19 2k 1k C12 R17 0.033 3.3k
Core : PQ20/16 Bobin : BPQ20/16-1114CP
10T 2T
10T
Vin 48V
+
2T
R16 5.1k
+ C13 470/10V
HA17431VP
C2 47/100V
C3 0.1
R10 15k
OUT(-)
D3 20V
L1 100
D1 IS2076A
C10+ 0.1
VREF 16
C9+ 4.7
D2 IS2076A
VCC 14
7T
VREF
R8 120k
REMOTE 15
REMOTE Comp.
22.2V
Vref Generator
UVL
300A
R9 120k
Vref Good
R Q Q
UVL
TDB Comp.
Vref good
0.5V
VREF
1.1V
Vref good
S
5A
Single End Comp.
10
S Q Q
TDB
8 C7 1000p
Vref good
SS Ramp
SS
SS Comp.
SS Ramp
R
TDB Latch
4V
Vcc
11
PGND
VREF
R12 OUT1 10
H5N2001LS
CT
VREF
RT
6
D Q
Driver
Vcc
R7 27k
CT
7
CK Q
C7 1000p
Vref good
1/2 Divider
13
12
R S Q Q
R11 OUT2 10
PGND
Oscillator
Blanking Pulse
IN
Vcc
CS Latch
OUT
65ns
VREF
5
CS Comp.
CS
R4 1k
400A
VREF
INM 2
E-Amp.
2R
R
9
C5 680p
SGND
R13 0.15/2W
R6 5.1k
R3 5.1k
INP
(VCOMP-2VF)/3
1
1.4V
3
4 CSLIM
Blanking Enable Comp.
VREF
EOUT
R5 5.1k
R1 15k R2 12k
VREF
C4 0.01
C14 6800p
Photo Coupler
Rev.3.00 Jan 30, 2007 page 23 of 24
HA16150T/P
Package Dimensions
19.20 20.00 Max 16 9
As of January, 2003
Unit: mm
1 1.3
1.11 Max
8
7.40 Max
6.30
0.51 Min
2.54 Min 5.06 Max
7.62
2.54 0.25
0.48 0.10
0.25 - 0.05
0 - 15
Package Code JEDEC JEITA Mass (reference value)
+ 0.13
DP-16 Conforms Conforms 1.07 g
JEITA Package Code P-TSSOP16-4.4x5-0.65
RENESAS Code PTSP0016JB-B
Previous Code TTP-16DA
MASS[Typ.] 0.05g
*1
D
F 9
16
bp
b1
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
HE
E
c1
Index mark
*2
Terminal cross section
1
Z
e
*3
c
8
bp
Reference Symbol
Dimension in Millimeters
x
M
L1
A1
L
y
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 5.00 5.30 4.40 0.03 0.07 0.10 1.10 0.15 0.22 0.30 0.20 0.12 0.17 0.22 0.15 0 8 6.20 6.40 6.60 0.65 0.13 0.10 0.65 0.40 0.50 0.60 1.0
Rev.3.00 Jan 30, 2007 page 24 of 24
A
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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